1. Field of the Invention
This invention relates generally to integrated circuits and more particularly to testing of integrated circuits.
2. Description of Related Art
Integrated circuit devices include millions of components and logic devices for executing particular functions. Such functions include data processing, signal manipulation, communications, etc. Additionally, demands are being made for flexible architectures that operate at throughput rates and efficiencies heretofore only realized by application specific integrated circuit designs. Such flexible architectures typically include a combination of programmable logic, fixed logic, and software driven processor based logic.
Such new systems, however, are very complex and require complex testing plans. Moreover, the increased throughput demands are pushing some current integrated circuit manufacturing processes to their operating limits. Integrated circuit processing limits (e.g., device parasitics, trace sizes, propagation delays, device sizes) and integrated circuit (IC) fabrication limits (e.g., IC layout, frequency response of the packaging, frequency response of bonding wires) limit the speed at which the high throughput integrated circuit may operate without excessive jitter performance or phase noise performance.
Modern integrated circuit systems, including high data rate communication systems, typically include a plurality of circuit boards that communicate with each other by way of signal traces, bundled data lines, back planes, etc. Accordingly, designers of high data rate communication transceiver devices often have conflicting design goals that relate to the performance of the particular device. For example, there are many different communication protocols specified for data rates that range from 2.48832 gigabits-per-second for OC48, to 9.95 gigabits-per-second for OC192. Other known standards define data rates of 2.5 gigabits-per-second (INFINIBAND) or 3.125 gigabits-per-second (XAUI). For example, one protocol may specify a peak voltage range of 200-400 millivolts, while another standard specifies a mutually exclusive voltage range of 500-700 millivolts. Thus, a designer either cannot satisfy these mutually exclusive requirements (and therefore cannot support multiple protocols) or must design a high data rate transceiver device that can adapt according to the protocol being used for the communications.
Along these lines, programmable logic devices, and more particularly, field programmable gate array (FPGA) circuits are gaining in popularity for providing the required flexibility and adaptable performance, as described above, for those designers who seek to build one device that can operate according to multiple configurations. For example, parallel interface buses such as Peripheral Component Interface (PCI) and the newer high-speed PCI (PCI-X) may be programmed for a computer interface while high-speed serial I/O may be programmed to be compatible with 3G-IO, InfiniBand, or Rapid IO. Thus, while FPGA technology affords a designer an opportunity to develop flexible and configurable hardware circuits, the opportunity has come with increasingly complex designs that increase the cost of production testing.
Testing every functional logic device and every routing resource within the FPGA or other dense logic device requires a large number of test designs that further require long sequences of test bit streams that are clocked into the FPGA or dense logic device. This leads to increased testing time and costs. There is a need, therefore, for a method and apparatus to reduce the number of test designs in a manner that will reduce the overall test bit stream programming time and, therefore, the cost of testing.